View HYB18M512160BFX_4100764.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

November 2006
HYB18M512160BFX-7.5
DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM RoHS compliant
Data S heet
Rev. 1.10
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
HYB18M512160BFX-7.5, ,
Revision History: 2006-11, Rev. 1.10 Page All Pg 49 Subjects (major changes since last revision) Qimonda Update
IDD6 is changed from 2.5mA to 2mA
Data Sheet
2
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Contents
1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.6 2.4.7 2.4.7.1 2.4.7.2 2.4.8 2.4.8.1 2.4.9 2.4.9.1 2.4.9.2 2.4.10 2.4.10.1 2.4.11 2.4.12 2.5 3 3.1 3.2 3.3 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor . . . . . . . . . . . . . . . . Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEEP POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLOCK STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8 9
10 10 11 11 12 12 12 14 14 15 15 16 17 18 18 19 20 21 25 26 26 27 28 32 33 35 35 36 36 36 38 39 39 40 40 44 44 46 49
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Data Sheet
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Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Command Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Inputs Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timing Parameters for Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing Parameters for ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Timing Parameters for READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Timing Parameters for WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timing Parameters for PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Timing Parameters for AUTO REFRESH and SELF REFRESH Commands . . . . . . . . . . . . . . . . . . . . . . . . . 37 Timing Parameters for POWER-DOWN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Minimum Number of Required Clock Pulses per Access Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Truth Table - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current State Bank n - Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current State Bank n - Command to Bank m (different bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Output Slew Rate Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 AC Overshoot / Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Maximum Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Data Sheet
4
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
List of Illustrations
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 8 Figure 10 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 33 Figure 35 Figure 37 Figure 38 Figure 39 Figure 40 Standard Ballout 512-Mbit DDR Mobile-RAM (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-Up Sequence and Mode Register Sets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address / Command Inputs Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bank Activate Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Basic READ Timing Parameters for DQs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 READ to WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Basic WRITE Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WRITE Burst (min. and max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 WRITE to WRITE (min. and max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Non-Consecutive WRITE to WRITE (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Random WRITE Cycles (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Non-Interrupting WRITE to READ (max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Interrupting WRITE to READ (Max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Non-Interrupting WRITE to PRECHARGE (Max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupting WRITE to PRECHARGE (Max. tDQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Self Refresh Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Clock Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AC Overshoot and Undershoot Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 P-VFBGA-60-1 (Plastic Very Thin Fine Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Data Sheet
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Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Overview
1
1.1
* * * * * * * * * * * * * * * * *
Overview
Features
4 banks x 8 Mbit x 16 organization Double-data-rate architecture : two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver DQS is edge-aligned with data for READs and center-aligned with data for WRITEs Differential clock input (CK / CK) Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS Four internal banks for concurrent operation Programmable CAS latency: 2 and 3 Programmable burst length: 2, 4, 8 and 16 Programmable drive strength (full, half, quarter) Auto refresh and self refresh modes 8192 refresh cycles / 64ms Auto precharge Commercial (0C to +70C) operating temperature range TS pad to support Super-Extended temperature range 60-ball Very Thin FBGA package (10.5 x 10.5 x 1.0 mm) RoHS Compliant Product1)
Power Saving Features * * * * * * Low supply voltages: VDD = 1.70 V - 1.90 V, VDDQ = 1.70 V - 1.90 V Optimized operating (IDD0 , IDD4), self refresh (IDD6) and standby currents (IDD2 , IDD3) DDR I/O scheme with no DLL Programmable Partial Array Self Refresh (PASR) Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Clock Stop, Power-Down and Deep Power-Down modes Performance - 7.5 CL = 3 CL = 2 Access Time (tACmax) Table 2 Item Banks Rows Columns Memory Addressing Scheme Addresses BA0, BA1 A0 - A12 A0 - A9 133 66 6.5 Unit MHz MHz ns
Table 1
Part Number Speed Code Clock Frequency (fCKmax)
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
6
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Overview Table 3 Type
1)
Ordering Information Package Description 133 MHz 4 Banks x 8 Mbit x 16 Low Power DDR SDRAM
Commercial Temperature Range HYB18M512160BFX-7.5 P-VFBGA-60-1
1) HYB: Designator for memory products (HYB: standard temp. range) 18M: 1.8V DDR Mobile-RAM 512: 512 MBit density 160: 16 bit interface width B: die revision F: green product -7.5: speed grades (min. clock cycle time)
1.2
Pin Configuration
1 2 DQ15 DQ13 DQ11 DQ9 UDQS UDM CK A11 A7 A4 3 7 A B C D E F G H J K 8 DQ0 DQ2 DQ4 DQ6 LDQS LDM CAS BA0 A0 A3 9
VSS VDDQ VSSQ VDDQ VSSQ VSS
CKE A9 A6
VSSQ
DQ14 DQ12 DQ10 DQ8 NC CK A12 A8 A5
VDDQ
DQ1 DQ3 DQ5 DQ7 NC WE CS A10/AP A2
VDD VSSQ VDDQ VSSQ VDDQ VDD
RAS BA1 A1
VSS
VDD
Figure 1
Standard Ballout 512-Mbit DDR Mobile-RAM (Top View)
Data Sheet
7
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Overview
1.3
Description
The HYB18M512160BFX is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The HYB18M512160BFX uses a double-data-rate architecture to achieve high-speed operation. The double-datarate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. The HYB18M512160BFX is especially designed for mobile applications. It operates from a 1.8V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep PowerDown (DPD) mode. For further power-savings the clock may be stopped during idle periods. The HYB18M512160BFX is housed in a 60-ball P-VFBGA package. It is available in Commercial (0C to 70C) temperature range.
CKE CK CK
Control Logic
Command Decode
CS RAS CAS WE
Bank 1
Bank 2
Bank 3
Bank 0 Row Address Latch & Decoder
Row Address Mux
Mode Registers
13
13
13
8192
Bank 0 Memory Array
(8192 x 512 x 32) CK/CK Data
Address Register
Read Latch
A0-A12 BA0,BA1
15
13
16
MUX
16
Drivers
Sense Amplifier
16
Refresh Counter
Bank Column Logic
32
2
IO Gating DQM Mask Logic
DQS Generator Input Reg. Recievers Write Mask FIFO 4 & Drivers 32
clk out clk in Data Col0 2 16 2 2
DQ0DQ15 UDM, LDM UDQS LDQS
2
10
Column Address Counter / Latch
9
Column Decoder
Col0
CK/CK
Note 1: The Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent the actual circuit implementation Note 2: UDM / LDM are unidirectional signals (input only), but internally loaded to match the load of the bidirectional DQ and UDQS / LDQS
Figure 2 Data Sheet
Functional Block Diagram 8 Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Overview
1.4
Table 4 Ball CK, CK CKE
Pin Definition and Description
Pin Description Type Input Input Detailed Function Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on crossing of the positive edge of CK and negative edge of CK. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides precharge powerdown and self refresh operation (all banks idle), or active power-down (row active in any bank). CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Data Inputs/Output: Bi-directional data bus (16 bit) Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data. LDQS corresponds to the data on DQ0 - DQ7; UDQS to the data on DQ8 - DQ15. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. DM may be driven HIGH, LOW, or floating during READs. LDM corresponds to the data on DQ0 - DQ7; UDM to the data on DQ8 - DQ15. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-code during a MODE REGISTER SET command.
CS
Input
RAS, CAS, WE DQ0 - DQ15 LDQS, UDQS LDM, UDM
Input I/O I/O
Input
BA0, BA1
Input
A0 - A12
Input
VDDQ VSSQ VDD VSS
N.C.
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: VDDQ = 1.70 V - 1.90 V Supply I/O Ground Supply Power Supply: Power for the core logic and input buffers, VDD = 1.70 V - 1.90 V Supply Ground - No Connect
Data Sheet
9
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2
Functional Description
The 512-Mbit DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.
2.1
Power On and Initialization
The DDR Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational procedures other than those specified may result in undefined operation.
Figure 3
Power-Up Sequence and Mode Register Sets
Data Sheet
10
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description 1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD and VDDQ are driven from a single power converter output. Assert and hold CKE to a HIGH level. 2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks. 3. Wait for 200s while issuing NOP or DESELECT commands. 4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period. 5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRFC period. 6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode Register, each followed by NOP or DESELECT commands for at least tMRD period; the order in which both registers are programmed is not important. Following these steps, the DDR Mobile-RAM is ready for normal operation.
2.2 2.2.1
Register Definition Mode Register
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. MR Mode Register Definition
BA1 0 BA0 0 A12 0 A11 0 A10 0 A9 0
(BA[1:0] = 00B)
A8 0 A7 0 A6 A5 CL A4 A3 BT A2 A1 BL A0
Field CL
Bits [6:4]
Type w
Description CAS Latency 010 2 011 3 Note: All other bit combinations are RESERVED. Burst Type 0 Sequential 1 Interleaved Burst Length 001 2 010 4 011 8 100 16 Note: All other bit combinations are RESERVED.
BT
3
w
BL
[2:0]
w
Data Sheet
11
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.2.1.1
Burst Length
READ and WRITE accesses to the DDR Mobile-RAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, 8 or 16 locations are available. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1 - A9 when the burst length is set to two, by A2 - A9 when the burst length is set to four, by A3 - A9 when the burst length is set to eight and by A4 - A9 when the burst length is set to sixteen. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
2.2.1.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 5.
2.2.1.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks. If a READ command is registered and the latency is 3 clocks, the first data element will be valid after (2 * tCK + tAC). If a READ command is registered and the latency is 2 clocks, the first data element will be valid after (tCK + tAC). For details please refer to the READ command description.
Data Sheet
12
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
Table 5 Burst Length 2 4
Burst Definition Starting Column Address A3 A2 A1 A0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Order of Accesses Within a Burst (Hexadecimal Notation) Sequential Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
8
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
16
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 -1 -2 -3 -4 - 5 - 6 - 7 - 8 - 9 - A - B - C - D - E - F 0 -1 -2 -3 - 4 - 5 - 6 - 7 - 8 - 9 - A - B - C - D - E - F 1 -2 -3 -4 -5 - 6 - 7 - 8 - 9 - A - B - C - D - E - F - 0 1 -0 -3 -2 - 5 - 4 - 7 - 6 - 9 - 8 - B - A - D - C - F - E 2 -3 -4 -5 -6 - 7 - 8 - 9 - A - B - C - D - E - F - 0 - 1 2 -3 -0 -1 - 6 - 7 - 4 - 5 - A - B - 8 - 9 - E - F - C - D 3 -4 -5 -6 -7 - 8 - 9 - A - B - C - D - E - F - 0 - 1 - 2 3 -2 -1 -0 - 7 - 6 - 5 - 4 - B - A - 9 - 8 - F -E - D - C 4 -5 -6 -7 -8 - 9 - A - B - C - D - E - F - 0 - 1 - 2 - 3 4 -5 -6 -7 - 0 - 1 - 2 - 3 - C - D - E - F - 8 - 9 - A - B 5 -6 -7 -8 -9 - A - B - C - D - E - F - 0 - 1 - 2 - 3 - 4 5 -4 -7 -6 - 1 - 0 - 3 - 2 - D - C - F - E - 9 - 8 - B - A 6 -7 -8 -9 -A - B - C - D - E - F - 0 - 1 - 2 - 3 - 4 - 5 6 -7 -4 -5 - 2 - 3 - 0 - 1 - E - F - C - D - A - B - 8 - 9 7 -8 -9 -A - B - C - D - E - F - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 -6 -5 -4 - 3 - 2 - 1 - 0 - F - E - D - C - B - A - 9 - 8 8 -9 -A - B - C - D - E - F - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 8 -9 -A - B - C - D - E - F - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 9 -A - B - C - D - E - F - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 9 -8 -B - A - D - C - F - E - 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 A - B -C - D - E - F - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 A - B - 8 - 9 - E - F - C - D - 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
Notes For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block. For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block. For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block. For a burst length of 16, A4-Ai select the sixteen-data-element block; A0-A3 select the first access within the block. 5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. 1. 2. 3. 4.
Data Sheet
13
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.2.2
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Address bits A0 - A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive Strength, while bits A7 - A12 shall be written to zero. Bits A3 and A4 are "don't care" (see below). Reserved states should not be used, as unknown operation or incompatibility with future versions may result. EMR Extended Mode Register
BA1 1 BA0 0 A12 0 A11 0 A10 0 A9 0
(BA[1:0] = 10B)
A8 0 A7 0 A6 DS A5 A4 A3 A2 A1 PASR A0
(TCSR)
Field DS
Bits [6:5]
Type w
Description Selectable Drive Strength 00 Full Drive Strength 01 Half Drive Strength 10 Quarter Drive Strength Note: All other bit combinations are RESERVED. Temperature Compensated Self Refresh XX Superseded by on-chip temperature sensor (see text) Partial Array Self Refresh 000 all banks 001 half array (BA1 = 0) 010 quarter array (BA1 = BA0 = 0) 101 1/8 array (BA1 = BA0 = RA12 = 0) 110 1/16 array (BA1 = BA0 = RA12 = RA11 = 0) Note: All other bit combinations are RESERVED.
TCSR [4:3] PASR [2:0]
w w
2.2.2.1
Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to DDR Mobile-RAMs. With PASR, self refresh may be restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by tREF (cf. Table 14).
Data Sheet
14
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.2.2.2
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. This refresh requirement heavily depends on the die temperature: high temperatures correspond to short refresh periods, and low temperatures correspond to long refresh periods. The DDR Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die temperature and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the TCSR bits in the Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and power-saving, because * * * it is fully compatible to all processors that do not support the Extended Mode Register it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the lack of an external temperature sensor it does not require any processor interaction for regular TCSR updates
2.2.2.3
Selectable Drive Strength
The drive strength of the DQ output buffers is selectable via bits A5 and A6. The "full drive strength" (default) is suitable for heavier loaded systems. The "half drive strength" is intended for lightly loaded systems or systems with reduced performance requirements. Finally, for systems with point-to-point connection, a "quarter drive strength" is available. I-V curves for full and half drive strengths are included in this document.
Data Sheet
15
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.3
State Diagram
Deep Power Down
Power applied
Power On
DPDSX
Precharge All Banks
DPDS REFSX
Self Refresh
Idle MRS EMRS
MRS
REFS REFA CKEL CKEH
All banks precharged
Auto Refresh
Active Power Down
CKEH CKEL
ACT
Precharge Power Down
Row Active
READ
Burst Stop
WRITE WRITE WRITEA
BST READA READ
READ
WRITE
READ
WRITEA
READA PRE PRE PRE
READA
WRITE A
READ A
PRE
Precharge PREALL Automatic Sequence Command Sequence
ACT = Active BST = Burst Terminate CKEL = Enter Power-Down CKEH = Exit Power-Down DPDS = Enter Deep Power-Down DPDSX = Exit Deep Power-Down
EMRS = Ext. Mode Reg. Set MRS = Mode Register Set PRE = Precharge PREALL = Precharge All Banks REFA = Auto Refresh REFS = Enter Self Refresh
REFSX = Exit Self Refresh READ = Read w/o Auto Precharge READA = Read with Auto Precharge WRITE = Write w/o Auto Precharge WRITEA = Write with Auto Precharge
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and commands to control them, not all details. In particular situations involving more than one bank are not captured in full detail.
Figure 4 Data Sheet
State Diagram 16 Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4
Table 6 Command NOP ACT RD WR BST PRE ARF MRS
1) 2) 3) 4) 5)
Commands
Command Overview CS H L L L L L L L L RAS CAS WE X H L H H H L L L X H H L L H H L L X H H H L L L H L Address X X Bank / Row Bank / Col Bank / Col X Code X Op-Code Notes
1)2) 1)2) 1)3) 1)4) 1)4) 1)5) 1)6) 1)7)8) 1)9)
DESELECT NO OPERATION ACTIVE (Select bank and row) READ (Select bank and column and start read burst) WRITE (Select bank and column and start write burst) BURST TERMINATE or DEEP POWER-DOWN PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH entry MODE REGISTER SET
6) 7) 8) 9)
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN. DESELECT and NOP are functionally interchangeable. BA0, BA1 provide the bank address, and A0 - A12 provide the row address. BA0, BA1 provide the bank address, A0 - A9 provide the column address; A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. This command is BURST TERMINATE if CKE is HIGH, DEEP POWER-DOWN if CKE is LOW. The BURST TERMINATE command is defined for READ bursts with Auto Precharge disabled only; it is undefined (and should not be used) for read bursts with Auto Precharge enabled, and for write bursts. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care". This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
Table 7
DM Operation DM L H DQs Notes Valid X
1) 1)
Name (Function) Write Enable Write Inhibit
1) Used to mask write data provided coincident with the corresponding data
Address (BA0, BA1, A0 - A12) and command inputs (CKE, CS, RAS, CAS, WE) are all registered on the crossing of the positive edge of CK and the negative edge of CK. Figure 5 shows the basic timing parameters, which apply to all commands and operations.
tCK CK CK tIS tIH Valid Valid Valid = Don't Care tCH tCL
Input
Figure 5 Data Sheet
Address / Command Inputs Timing Parameters 17 Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
Table 8 Parameter
Inputs Timing Parameters1) Symbol tCH tCL tCK tIS tIH tIPW - 7.5 Unit Notes Min. Max. 0.45 0.55 tCK - 0.45 0.55 tCK - 7.5 - ns 2) 15 - 1.3 - ns 3)4)5) 3)6) 1.5 - 1.3 - ns 3)4) 3)6) 1.5 - 3.0 - ns 7)
Clock high-level width Clock low-level width Clock cycle time Address and control input setup time Address and control input hold time Address and control input pulse width
1) 2) 3) 4) 5) 6) 7)
CL = 3 CL = 2 fast slew rate slow slew rate fast slew rate slow slew rate
All AC timing characteristics assume an input slew rate of 1.0 V/ns. The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes. The transition time for address and command inputs is measured between VIH and VIL. For command / address input slew rate 1V/ns. A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter. For command / address input slew rate 0.5 V/ns and < 1.0 V/ns. This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
2.4.1
NO OPERATION (NOP)
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care (High)
The NO OPERATION (NOP) command is used to perform a NOP to a DDR Mobile-RAM which is selected (CS = LOW). This prevents unwanted commands from being registered during idle states. Operations already in progress are not affected.
Figure 6
No Operation Command
2.4.2
DESELECT
The DESELECT function (CS = HIGH) prevents new commands from being executed by the DDR Mobile-RAM. The DDR Mobile-RAM is effectively deselected. Operations already in progress are not affected.
Data Sheet
18
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.3
MODE REGISTER SET
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 Code Code = Don't Care (High)
The Mode Register and Extended Mode Register are loaded via inputs A0 - A12 (see mode register descriptions in Chapter 2.2). The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.
Figure 7
Mode Register Set Command
CK CK Command MRS NOP tMRD Address Code Valid = Don't Care Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0 - A12) Valid
Figure 8 Table 9 Parameter
Mode Register Definition Timing Parameters for Mode Register Set Command Symbol tMRD - 7.5 Unit Notes Min. Max. 2 - tCK -
MODE REGISTER SET command period
Data Sheet
19
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.4
ACTIVE
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 RA BA = Don't Care
BA = Bank Address RA = Row Address
(High)
Before any READ or WRITE commands can be issued to a bank within the DDR Mobile-RAM, a row in that bank must be "opened" (activated). This is accomplished via the ACTIVE command and addresses BA0, BA1, A0 - A12 (see Figure 9), which decode and select both the bank and the row to be activated. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
Figure 9
ACTIVE Command
CK CK Command A0-A12 BA0, BA1 ACT Row BA x tRRD NOP ACT Row BA y tRCD NOP NOP RD/WR Col BA y NOP
= Don't Care
Figure 10
Bank Activate Timings
Table 10 Parameter
Timing Parameters for ACTIVE Command Symbol tRC tRCD tRRD - 7.5 Unit Notes Min. Max. 65 - ns 1) 22.5 - ns 1) 15 - ns 1)
ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period ; round to the next higher integer.
Data Sheet
20
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.5
READ
CK CK CKE CS RAS CAS WE A0-A9 A10 BA0,BA1 CA
Enable AP
READ bursts are initiated with a READ command, as shown in Figure 11.
(High)
Basic timings for the DQs are shown in Figure 12; they apply to all read operations. The starting column and bank addresses are provided with the READ command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed will start precharge at the completion of the burst, provided tRAS has been satisfied. For the generic READ commands used in the following illustrations, Auto Precharge is disabled.
AP
Disable AP
BA = Don't Care
BA = Bank Address CA = Column Address AP = Auto Precharge
Figure 11
READ Command
tCK tCK tCH tCL
CK CK
tACmax
DQS
tDQSCK tRPRE tAC tDQSQmax DO n tQH
tDQSCK
tRPST tHZ
DQ
tLZ
DO n+1 DO n+2 DO n+3 tQH tDQSCK
tACmin
DQS tRPRE
tDQSCK
tRPST tHZ
tAC DQ tLZ
tDQSQmax DO n tQH
DO n+1 DO n+2 DO n+3 tQH
DO n = Data Out from column n = Don't Care Burst Length = 4 in the case shown CAS Latency = 3 in the case shown All DQ are valid tAC after the CK edge. All DQ are valid tDQSQ after the DQS edge, regardless of tAC
Figure 12 Data Sheet
Basic READ Timing Parameters for DQs 21 Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
Table 11 Parameter
Timing Parameters for READ Command Symbol tAC tDQSCK tLZ tHZ tDQSQ tQH tQHS tRPRE tRPST tRAS tRC tRCD tRP - 7.5 Min. 2.0 2.0 1.0 - - tHP-tQHS - 0.9 0.7 0.4 45 65 22.5 22.5 Max. 6.5 6.5 - 6.5 0.6 - 0.75 1.1 1.1 0.6 70,000 - - - Unit ns ns ns ns ns ns ns tCK tCK ns ns ns ns Notes
1)2) 1)2) 3) 3) 4) 5) 5)
DQ output access time from CK/CK DQS output access time from CK/CK DQ & DQS low-impedance time from CK/CK DQ & DQS high-impedance time from CK/CK DQS - DQ skew DQ / DQS output hold time from DQS Data hold skew factor Read preamble CL = 3 CL = 2 Read postamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay PRECHARGE command period
- -
6) 6) 6) 6)
1) The output timing reference level is VDDQ/2. 2) Parameters tAC and tQH are specified for full drive strength and a reference load of 20pF. This reference load is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive strength with a nominal load of 10pF parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is suggested. 3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 4) tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 5) tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 6) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period ; round to the next higher integer.
During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. The diagrams in Figure 13 show general timing for each supported CAS latency setting. DQS is driven by the DDR Mobile-RAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other READ commands have been initiated, the DQs will go High-Z.
Data Sheet
22
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n NOP NOP NOP NOP NOP
= Don't Care DO n = Data Out from column n BA, Col n = Bank A, Column n Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 13
READ Burst
Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in Figure 14.
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n DO b DO b NOP READ BA,Col b NOP NOP NOP
= Don't Care DO n (or b) = Data Out from column n (or column b) Burst Length = 4, 8 or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7 or 15) subsequent elements of Data Out appear in the programmed order following DO b Read commands shown must be to the same device
Figure 14
Consecutive READ Bursts
Data Sheet
23
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive READ data is illustrated in Figure 15.
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n DO b NOP NOP READ BA,Col b NOP NOP
= Don't Care DO n (or b) = Data Out from column n (or column b) BA A Col n (b) = Bank A, Column n (b) Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n (b)
Figure 15
Nonconsecutive READ Bursts
Full-speed random READ accesses (Burst Length = 2, 4, 8 or 16) within a page (or pages) can be performed as shown in Figure 16.
CK CK Command Address READ BA,Col n READ BA,Col x CL=2 DQS DQ DO n CL=3 DQS DQ DO n DO n' DO x DO x' DO b DO b' DO n' DO x DO x' DO b DO b' DO g DO g' READ BA,Col b READ BA,Col g NOP NOP
DO n, etc. = Data Out from column n, etc. n', x', etc. = Data Out elements, according to the programmed burst order BA, Col n = Bank A, Column n Burst Length = 2, 4, 8 or 16 in cases shown (if burst of 4, 8 or 16, the burst is interrupted) Reads are to active rows in any banks
= Don't Care
Figure 16
Random READ Accesses
Data Sheet
24
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.5.1
READ Burst Termination
Data from any READ burst may be truncated using the BURST TERMINATE command (see Figure 20), provided that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command should be issued x clock cycles after the READ command, where x equals the number of desired data element pairs. This is shown in Figure 17.
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n = Don't Care NOP BST NOP NOP NOP
DO n = Data Out from column n BA, Col n = Bank A, Column n Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 17
Terminating a READ Burst
Data Sheet
25
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.5.2
READ to WRITE
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 18.
CK CK Command Address READ BA,Col n CL=2 DQS DQ DM DO n Di b BST NOP WRITE BA,Col b tDQSS NOP NOP
Command Address
READ BA,Col n
BST
NOP
NOP
WRITE BA,Col b
NOP
CL=3 DQS DQ DM DO n = Data Out from column n; DI b = Data In to column b 1 subsequent element of Data Out appear in the programmed order following DO n. Data In elements are applied following DI b in the programmed order = Don't Care DO n Di b
Figure 18
READ to WRITE
2.4.5.3
READ to PRECHARGE
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank (provided that Auto Precharge was not activated). The PRECHARGE command should be issued x clock cycles after the READ command, where x equals the number of desired data element pairs. This is shown in Figure 19. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Please note that part of the row precharge time is hidden during the access of the last data elements. In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same READ burst with Auto Precharge enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts.
Data Sheet
26
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
CK CK Command Address READ BA,Col n CL=2 DQS DQ DO n CL=3 DQS DQ DO n NOP PRE Bank (a or all) tRP NOP NOP ACT BA, Row
= Don't Care DO n = Data Out from column n Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8 or 16 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL / 2) tCK after the READ command. Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks. The ACTIVE command may be applied if tRC has been met.
Figure 19
READ to PRECHARGE
2.4.6
BURST TERMINATE
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care (High)
The BURST TERMINATE command is used to truncate READ bursts (with Auto Precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in Figure 17.
Figure 20
BURST TERMINATE Command
Data Sheet
27
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.7
WRITE
CK CK CKE CS RAS CAS WE A0-A9 A10 BA0,BA1 CA
Enable AP
WRITE bursts are initiated with a WRITE command, as shown in Figure 21. Basic timings for the DQs are shown in Figure 22; they apply to all write operations.
(High)
The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge is disabled.
AP
Disable AP
BA = Don't Care
BA = Bank Address CA = Column Address AP = Auto Precharge
Figure 21
WRITE Command
tCK tCH tCL
CK CK Case 1: tDQSS = min DQS tWPRES tDQSS
tDQSH
tDSH
tDSH tWPST
tWPRE tDS tDH DI n
tDQSL
DQ, DM Case 2: tDQSS = max DQS tWPRES
tDQSS
tDQSH
tDSS tWPST
tDSS
tWPRE tDS tDH DI n
tDQSL
DQ, DM
DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n. Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the 25% window of the corresponding positive clock edge.
= Don't Care
Figure 22 Data Sheet
Basic WRITE Timing Parameters for DQs 28 Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
Table 12 Parameter
Timing Parameters for WRITE Command Symbol
- 7.5 Unit Notes Min. Max. DQ and DM input setup time fast slew rate tDS 0.75 - ns 1)2)3) 1)2)4) slow slew rate 0.85 - DQ and DM input hold time fast slew rate tDH 0.75 - ns 1)2)3) 1)2)4) slow slew rate 0.85 - DQ and DM input pulse width tDIPW 1.7 - ns 5) Write command to 1st DQS latching transition tDQSS 0.75 1.25 tCK - DQS input high-level width tDQSH 0.4 0.6 tCK - DQS input low-level width tDQSL 0.4 0.6 tCK - DQS falling edge to CK setup time tDSS 0.2 - tCK - DQS falling edge hold time from CK tDSH 0.2 - tCK - Write preamble setup time tWPRES 0 - ns 6) Write postamble tWPST 0.4 0.6 tCK 7) Write preamble tWPRE 0.25 - tCK - ACTIVE to PRECHARGE command period tRAS 45 70,000 ns 8) ACTIVE to ACTIVE command period tRC 65 - ns 8) ACTIVE to READ or WRITE delay tRCD 22.5 - ns 8) WRITE recovery time tWR 15 - ns 8) Internal write to Read command delay tWTR 1 - tCK - PRECHARGE command period tRP 22.5 - ns 8) 1) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
2) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 3) Input slew rate 1.0 V/ns.. 4) Input slew rate 0.5V/ns and < 1.0 V/ns. 5) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test. 6) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 7) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 8) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period ; round to the next higher integer.
During WRITE bursts, the first valid data-in element is registered on the first rising edge of DQS following the WRITE command, and subsequent data elements are registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of a clock cycle). The diagrams in Figure 23 show the two extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data is ignored.
Data Sheet
29
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
CK CK Command Address WRITE BA,Col b tDQSSmin DQS DQ DM tDQSSmax DQS DQ DM DI b = Data In to column b. 3 subsequent elements of Data In are applied in the programmed order following DI b. A non-interrupted burst of 4 is shown. A10 is LOW with the WRITE command (Auto Precharge is disabled) Di b Di b NOP NOP NOP NOP NOP
= Don't Care
Figure 23
WRITE Burst (min. and max. tDQSS)
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any clock cycle following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued x clock cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Figure 24 shows concatenated WRITE bursts of 4.
Data Sheet
30
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
CK CK Command Address WRITE BA,Col b tDQSSmin DQS DQ DM tDQSSmax DQS DQ DM DI b (n) = Data In to column b (column n) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. Non-interrupted bursts of 4 are shown. Each WRITE command may be to any active bank Di b Di n Di b Di n NOP WRITE BA,Col n NOP NOP NOP
= Don't Care
Figure 24
WRITE to WRITE (min. and max. tDQSS)
An example of non-consecutive WRITEs is shown in Figure 25.
CK CK Command Address DQS DQ DM DI b (n) = Data In to column b (or column n). 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. Non-interrupted bursts of 4 are shown. Each WRITE command may be to any active bank and may be to the same or different devices. Di b Di n WRITE BA,Col b tDQSSmax NOP NOP WRITE BA,Col n NOP NOP
= Don't Care
Figure 25
Non-Consecutive WRITE to WRITE (max. tDQSS)
Data Sheet
31
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description Full-speed random WRITE accesses within a page or pages can be performed as shown in Figure 26.
CK CK Command Address DQS DQ DM DI b etc. = Data In to column b, etc. . = Don't Care b', etc. = the next Data In following DI b, etc. according to the programmed burst order Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4, 8 or 16, burst would be truncated. Each WRITE command may be to any active bank and may be to the same or different devices. Di b Di b' Di x Di x' Di n Di n' Di a Di a' WRITE BA,Col b WRITE BA,Col x tDQSSmax WRITE BA,Col n WRITE BA,Col a WRITE BA,Col g NOP
Figure 26
Random WRITE Cycles (max. tDQSS)
2.4.7.1
WRITE to READ
Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR (WRITE to READ) should be met as shown in Figure 27.
CK CK Command Address DQS DQ DM DI b = Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b. A non-interrupted burst of 4 is shown. tWTR is referenced from the positive clock edge after the last Data In pair. A10 is LOW with the WRITE command (Auto Precharge is disabled) The READ and WRITE commands are to the same device but not necessarily to the same bank. Di b WRITE BA,Col b tDQSSmax tWTR NOP NOP NOP READ BA,Col n CL=3 NOP NOP
= Don't Care
Figure 27
Non-Interrupting WRITE to READ (max. tDQSS)
Data Sheet
32
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 28. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in Figure 28.
CK CK Command Address DQS DQ DM DI b = Data In to column b. DO n = Data Out from column n. An interrupted burst of 4 is shown, 2 data elements are written. 3 subsequent elements of Data In are applied in the programmed order following DI b. tWTR is referenced from the positive clock edge after the last Data In pair. A10 is LOW with the WRITE command (Auto Precharge is disabled) The READ and WRITE commands are to the same device but not necessarily to the same bank. Di b DO n WRITE BA,Col b tDQSSmax tWTR NOP NOP READ BA,Col n CL=3 NOP NOP NOP
= Don't Care
Figure 28
Interrupting WRITE to READ (Max. tDQSS)
2.4.7.2
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in Figure 29.
CK CK Command Address DQS DQ DM DI b = Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b. A non-interrupted burst of 4 is shown. tWR is referenced from the positive clock edge after the last Data In pair. A10 is LOW with the WRITE command (Auto Precharge is disabled) Di b WRITE BA,Col b tDQSSmax tWR NOP NOP NOP NOP PRE BA a (or all)
= Don't Care
Figure 29
Non-Interrupting WRITE to PRECHARGE (Max. tDQSS)
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure 30. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any
Data Sheet
33
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description subsequent data in should be masked with DM. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a WRITE burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts.
CK CK Command Address DQS DQ DM Di b *1 *1 *1 *1 = Don't Care WRITE BA,Col b tDQSSmax tWR *2 NOP NOP NOP PRE BA a (or all) NOP
DI b = Data In to column b . An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written. tWR is referenced from the positive clock edge after the last desired Data In pair. A10 is LOW with the WRITE command (Auto Precharge is disabled) *1 = can be Don't Care for programmed burst length of 4 *2 = for programmed burst length of 4, DQS becomes Don't Care at this point
Figure 30
Interrupting WRITE to PRECHARGE (Max. tDQSS)
Data Sheet
34
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.8
PRECHARGE
CK CK CKE CS RAS CAS WE A0-A9 A11,A12
All Banks
(High)
The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open rows in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
A10
One Bank
BA0,BA1
BA = Don't Care
BA = Bank Address (if A10 = L, otherwise Don't Care)
Figure 31 Table 13 Parameter
PRECHARGE Command Timing Parameters for PRECHARGE Command Symbol tRAS tRP tWR - 7.5 Unit Notes Min. Max. 45 70,000 ns 1) 22.5 - ns 1) 15 - ns 1)
ACTIVE to PRECHARGE command period PRECHARGE command period WRITE recovery time
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period ; round to the next higher integer.
2.4.8.1
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type.
Data Sheet
35
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.9
AUTO REFRESH and SELF REFRESH
The DDR Mobile-RAM requires a refresh of all rows in an rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode. Dividing the number of rows into the rolling 64ms interval defines the average refresh interval, tREFI, which is a guideline to controllers for distributed refresh timing.
2.4.9.1
AUTO REFRESH
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care (High)
Auto Refresh is used during normal operation of the DDR Mobile-RAM. The command is nonpersistent, so it must be issued each time a refresh is required. A minimum time tRFC is required between two AUTO REFRESH commands. The same rule applies to any access command after the Auto Refresh operation. All banks must be precharged prior to the AUTO REFRESH command. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The DDR Mobile-RAM requires Auto Refresh cycles at an average periodic interval of tREFI (max.). Partial array mode has no influence on Auto Refresh mode.
Figure 32
AUTO REFRESH Command
To allow for improved efficiency in scheduling and switching between tasks, some fexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to the DDR Mobile-RAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
CK CK Command Address A10 (AP) DQ Pre All
High-Z
tRP PRE NOP ARF
tRFC NOP NOP ARF
tRFC NOP NOP ACT Ba A, Row n Row n
Ba A, Row n = Bank A, Row n
= Don't Care
Figure 33
Auto Refresh
2.4.9.2
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR Mobile-RAM, even if the rest of the system is powered down. When in the Self Refresh mode, the DDR Mobile-RAM retains data without external clocking. The DDR Mobile-RAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except CKE are "Don't Care" during Self Refresh. The user may halt the external clock one clock after Self Refresh entry is registered. Data Sheet 36 Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. The device executes a minimum of one AUTO REFRESH command internally once it enters Self Refresh mode. The clock is internally disabled during Self Refresh operation to save power. The minimum time that the device must remain in Self Refresh mode is tRFC. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXS must be satisfied before a valid command can be issued to the device to allow for completion of any internal refresh in progress.
= Don't Care
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1
Figure 34
SELF REFRESH Entry Command
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH command is recommended.
CK CK tRP CKE Command Address A10 (AP) DQ Pre All
High-Z
> tRFC
tXSR
tRFC
PRE
NOP
ARF
NOP
NOP
NOP
ARF
NOP
ACT Ba A, Row n Row n
Enter Self Refresh Mode
Exit from Self Refresh Mode
Any Command (Auto Refresh Recommended)
= Don't Care
Figure 35 Table 14 Parameter
Self Refresh Entry and Exit Timing Parameters for AUTO REFRESH and SELF REFRESH Commands Symbol tRFC tRP tXSR tREF tREFI - 7.5 Unit Notes Min. Max. 75 - ns 1) 22.5 - ns 1) 120 - ns 1) - 64 ms - - 7.8 s 2)
AUTO REFRESH to ACTIVE/AUTO REFRESH command period PRECHARGE command period Self refresh exit to next valid command delay Refresh period Average periodic refresh interval (8192 rows)
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period ; round to the next higher integer. 2) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8 * tREFI.
Data Sheet
37
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.10
POWER-DOWN
CK CK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. In power-down mode, CKE LOW must be maintained, and all other input signals are "Don't Care". The minimum power-down duration is specified by tCKE. However, power-down duration is limited by the refresh requirements of the device. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). A valid command may be applied tXP after exit from power-down.
Figure 36
Power-Down Entry Command
A minimum CKE high time of tCKE is required between two consecutive power-down states.
Figure 37 Table 15 Parameter
Power-Down Entry and Exit Timing Parameters for POWER-DOWN Symbol tXP tCKE - 7.5 Min. tCK+ tIS 2 Max. - - Unit Notes ns tCK
Exit power down delay CKE minimum high or low time
-
Data Sheet
38
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
2.4.10.1
DEEP POWER-DOWN
Deep Power-Down mode is a unique feature of DDR Mobile-RAMs for extremely low power consumption. Deep Power-Down mode is entered using the BURST TERMINATE command (cf Table 6) except that CKE is LOW. All internal voltage generators are stopped and all memory data is lost in this mode. To enter the Deep Power-Down mode all banks must be precharged. The Deep Power-Down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command sequence as for power-up initialization, including the 200s intial pause, has to be applied before any other command may be issued (cf. Figure 4).
2.4.11
CLOCK STOP
Stopping the clock during idle periods is a very effective method to reduce power consumption. The DDR MobileRAM supports clock stop in case: * the last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any data-out during read bursts; the number of clock pulses per access command depends on the device's AC timing parameters and the clock frequency (see Table 16); the related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met; CKE is held HIGH.
* *
When all conditions have been met, the device is either in "idle" or "row active" state (cf. Figure 4), and clock stop mode may be entered with CK held LOW and CK held HIGH. Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics. Figure 38 illustrates the clock stop mode: * * * * * initially the device is in clock stop mode; the clock is restarted with the rising edge of T0 and a NOP on the command inputs; with T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this access command has completed; Tn is the last clock pulse required by the access command latched with T1 the timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse required by this command and the clock is then stopped.
T0 T1 T2 Tn
CK CK CKE
Timing Condition Command
NOP CMD NOP NOP NOP
Clock Stopped
Exit Clock Stop
Valid Command
Enter Clock Stop
= Don't Care
Figure 38
Clock Stop
Data Sheet
39
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
Table 16
Minimum Number of Required Clock Pulses per Access Command Timing Condition tRCD (BL / 2) + CL [(BL / 2) + tRP] ; [(BL / 2) + CL] 1 + (BL / 2) + tWR 1 + (BL / 2) + tDAL tRP tRFC tMRD - 7.5 3 5 5 5 8 3 10 2 Unit tCK tCK tCK tCK tCK tCK tCK tCK Notes
1) 1)2) 1)2)3) 1)2) 1)2) 1) 1)
Command ACTIVE READ (Auto-Precharge Disabled) READ (Auto-Precharge Enabled) WRITE (Auto-Precharge Disabled) WRITE (Auto-Precharge Enabled) PRECHARGE AUTO REFRESH MODE REGISTER SET
1) These parameters depend on the operating frequency; the number of clock cycles shown are calculated for a clock frequency of 133 MHz for -7.5. 2) The values apply for a burst length of 4 and a CAS latency of 3. 3) Both timing conditions need to be satisfied; if not equal, the larger value applies
2.4.12
Clock Frequency Change
Depending on system considerations, it might be desired to change the DDR Mobile-RAM's clock frequency while the device is powered up. The DDR Mobile-RAM supports a clock frequency change when the device is in: * * * self refresh mode (see Figure 35); power-down mode (see Figure 37); clock stop mode (see Figure 38).
Once the clock runs stable at the new clock frequency, the timing conditions for exiting these states have to be met before applying the next access command. It should be pointed out that a continuous frequency drift is not considered a stable clock and therefore is not supported.
2.5
Table 17 CKEn-1 L
Function Truth Tables
Truth Table - CKE CKEn L Current State Power-Down Self Refresh Deep Power-Down L H Power-Down Self Refresh Deep Power-Down H L All Banks Idle Bank(s) Active All Banks Idle All Banks Idle H H Command X X X DESELECT or NOP DESELECT or NOP X DESELECT or NOP DESELECT or NOP AUTO REFRESH BURST TERMINATE Action Maintain Power-Down Maintain Self Refresh Maintain Deep Power-Down Exit Power-Down Exit Self Refresh Exit Deep Power-Down Enter Precharge Power-Down Enter Active Power-Down Enter Self Refresh Enter Deep Power-Down Notes
1)2)3)4) 1) to 4) 1) to 4) 1) to 5) 1) to 5) 1) to 4), 6) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4)
see Table 18 and Table 19
1) 2) 3) 4) 5) 6)
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state immediately prior to clock edge n. COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during tXP or tXSR period. Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
Data Sheet
40
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
Table 18 Any Idle
Current State Bank n - Command to Bank n CS H L L L L RAS CAS WE Command / Action X H L L L H H L H H L H H H L X H H L L L L H L L H H L L H X H H H L H L L H L L L H L L DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) ACTIVE (select and activate row) AUTO REFRESH MODE REGISTER SET READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) READ (truncate Read and start new Read burst) WRITE (truncate Read and start new Write burst) PRECHARGE (truncate Read and start Precharge) BURST TERMINATE READ (truncate Write and start Read burst) WRITE (truncate Write and start Write burst) PRECHARGE (truncate Write burst, start Precharge) Notes
1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 7) 1) to 7) 1) to 6), 8) 1) to 6), 8) 1) to 6), 9) 1) to 6), 8) 1) to 6), 8), 10) 1) to 6), 9) 1) to 6), 11) 1) to 6), 8), 12) 1) to 6), 8) 1) to 6), 9),12)
Current State
Row Active
L L L
Read (AutoPrecharge Disabled) Write (AutoPrecharge
L L L L L L L
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17) and after tXP or tXSR has been met (if the previous state was power-down or self refresh). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 19. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank is in the "idle" state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read with AP Enabled: Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write with AP Enabled: Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. 5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR Mobile-RAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the DDR Mobile-RAM is in the "all banks idle" state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks are in the idle state.
Data Sheet
41
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 9) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 10) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 11) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 12) Requires appropriate DM masking.
Table 19 Any Idle
Current State Bank n - Command to Bank m (different bank) CS H L X L L L L L L L L L L L L L L L L L L L L RAS CAS WE Command / Action X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) Any command otherwise allowed to bank m ACTIVE (select and activate row) READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) Notes
1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 6) 1) to 7) 1) to 7) 1) to 6) 1) to 6) 1) to 7) 1) to 8) 1) to 6) 1) to 6) 1) to 7), 9) 1) to 7) 1) to 6) 1) to 6) 1) to 7) 1) to 8) 1) to 6) 1) to 6) 1) to 7) 1) to 7)
Current State
Row Activating, Active, or Precharging
Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (with AutoPrecharge) Write (with AutoPrecharge)
1) to 6) PRECHARGE (Deactivate row in bank or banks) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17) and after tXP or tXSR has been met (if the
previous state was power-down or self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
Data Sheet
42
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Functional Description
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with AP Enabled: see following text. Write with AP Enabled: see following text. 3a. The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided). 4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 9) Requires appropriate DM masking.
Data Sheet
43
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3
3.1
Table 20 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Min. Values Max. 2.7 2.7 V V V V C C W mA -0.3 -0.3 -0.3 -0.3 0 -55 - - Unit
Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Commercial
VDD VDDQ VIN VOUT TC TSTG PD IOUT
VDDQ + 0.3 VDDQ + 0.3
+70 +150 0.7 50
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 21 Parameter Input capacitance: CK, CK Delta input capacitance: CK, CK Input capacitance: all other input-only pins Delta input capacitance: all other input-only pins Input/output capacitance: DQ, DQS, DM Delta input/output capacitance: DQ, DQS, DM Pin Capacitances1)2)3) Symbol Min. Values Max. 2.5 0.25 2.5 0.5 4.5 0.5 pF pF pF pF pF pF 1.5 - 1.5 - 3.5 - Unit
CI1 CDI1 CI2 CDI2 CIO CDIO
1) These values are not subject to production test but verified by device characterization. 2) Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD, VDDQ are applied and all other pins (except the pin under test) are floating. DQ's should be in high impedance state. This may be achieved by pulling CKE to low level. 3) Although DM is an input-only pin, it's input capacitance models the input capacitance of the DQ and DQS pins.
Data Sheet
44
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Electrical Characteristics
Table 22 Parameter
Electrical Characteristics1)2) Symbol Min. Values Max. 1.90 1.90 1.0 1.5 V V A A V V V V V V V V V V V V - - - - - - -
3) 3) 4)
Unit Notes
Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input leakage current Output leakage current Input high voltage Input low voltage Clock Inputs (CK, CK) DC input voltage DC input differential voltage AC input differential voltage AC differential cross point voltage DC input high voltage DC input low voltage AC input high voltage AC input low voltage Data Outputs (DQ0 - DQ15, LDQS, UDQS) Output high voltage
VDD VDDQ IIL IOL VIH VIL VIN VID(DC) VID(AC) VIX VIHD(DC) VILD(DC) VIHD(AC) VILD(AC) VOH VOL
1.70 1.70 -1.0 -1.5 0.8 x VDDQ -0.3 -0.3 0.4 x VDDQ 0.6 x VDDQ 0.4 x VDDQ 0.7 x VDDQ -0.3 0.8 x VDDQ -0.3 0.9 x VDDQ -
Address and Command Inputs (BA0, BA1, A0 - A12, CKE, CS, RAS, CAS, WE)
VDDQ + 0.3 0.2 x VDDQ
VDDQ + 0.3
VDDQ + 0.6 VDDQ + 0.6 0.6 x VDDQ VDDQ + 0.3
0.3 x VDDQ
Data Inputs (DQ0 - DQ15, LDM, UDM, LDQS, UDQS) - - - - - -
VDDQ + 0.3 0.2 x VDDQ
- 0.1 x VDDQ
Output low voltage 1) 0 C TC 70 C (comm.); All voltages referenced to VSS. VSS and VSSQ must be at same potential.
2) See Table 25 and Figure 39 for overshoot and undershoot definition. 3) VID is the magnitude of the difference between the input level on CK and the input level on CK. 4) The value of VIX is expected to be equal to 0.5 x VDDQ and must track variations in the DC level.
Data Sheet
45
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3.2
Table 23 Parameter
AC Characteristics
AC Characteristics1)2)3)4) Symbol tAC tDQSCK tCH tCL tHP tCK tDS tDH tDIPW tIS tIH tIPW tLZ tHZ tDQSQ tQH tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRES tWPST tWPRE tRPRE tRPST tRAS tRC tRFC tRCD tRP tRRD tWR tDAL - 7.5 Unit Notes Min. Max. 2.0 6.5 ns 5)6) 2.0 6.5 ns 5)6) 0.45 0.55 tCK - 0.45 0.55 tCK - min(tCL,tCH) ns 7)8) 7.5 - ns 9) 15 - 0.75 - ns 10)11)12) 10)11)13) 0.85 - 0.75 - ns 10)11)12) 10)11)13) 0.85 - 1.7 - ns 14) 1.3 - ns 12)15)16) 13)15)16) 1.5 - 1.3 - ns 12)15)16) 13)15)16) 1.5 - 3.0 - ns 14) 1.0 - ns 17) - 6.5 ns 17) - 0.6 ns 18) tHP-tQHS - ns 8) - 0.75 ns 8) 0.75 1.25 tCK - 0.4 0.6 tCK - 0.4 0.6 tCK - 0.2 - tCK - 0.2 - tCK - 2 - tCK - 0 - ns 19) 0.4 0.6 tCK 20) 0.25 - tCK - 0.9 1.1 tCK 21) 0.7 1.1 0.4 0.6 tCK - 45 70,000 ns 22) 65 - ns 22) 75 - ns 22) 22.5 - ns 22) 22.5 - ns 22) 15 - ns 22) 15 - ns 22) tCK 23) Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
DQ output access time from CK/CK DQS output access time from CK/CK Clock high-level width Clock low-level width Clock half period Clock cycle time DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Address and control input setup time Address and control input hold time Address and control input pulse width DQ & DQS low-impedance time from CK/CK DQ & DQS high-impedance time from CK/CK DQS - DQ skew DQ / DQS output hold time from DQS Data hold skew factor Write command to 1st DQS latching transition DQS input high-level width DQS input low-level width DQS falling edge to CK setup time DQS falling edge hold time from CK MODE REGISTER SET command period Write preamble setup time Write postamble Write preamble Read preamble
CL = 3 CL = 2 fast slew rate slow slew rate fast slew rate slow slew rate fast slew rate slow slew rate fast slew rate slow slew rate
CL = 3 CL = 2
Read postamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B delay WRITE recovery time Auto precharge write recovery + precharge time
Data Sheet
46
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Electrical Characteristics Table 23 Parameter AC Characteristics1)2)3)4) (cont'd) Symbol Unit Notes tCK - ns 22) ns tCK - ms - s 24)
- 7.5 Min. Max. 1 - Internal write to Read command delay tWTR Self refresh exit to next valid command delay tXSR 120 - Exit power down delay tXP tCK+ tIS - CKE minimum high or low time tCKE 2 - Refresh period tREF - 64 Average periodic refresh interval (8192 rows) tREFI - 7.8 1) 0 C TC 70 C (comm.); VDD = VDDQ = 1.70 V - 1.90 V. All voltages referenced to VSS.
2) All parameters assume proper device initialization. 3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VDDQ/2. 4) All AC timing characteristics assume an input slew rate of 1.0 V/ns. 5) The output timing reference level is VDDQ/2. 6) Parameters tac and tDQSCK are specified for full drive strength and a reference load as shown below. This circuit is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive strength with a nominal load of 10pF parameters tAC and tDQSCK are expected to be in the same range. However, these parameters are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is suggested.
I/O Z0 = 50 Ohms 20 pF
7) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 8) tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 9) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes. 10) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling). 11) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 12) Input slew rate 1.0 V/ns.. 13) Input slew rate 0.5V/ns and < 1.0 V/ns. 14) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test. 15) The transition time for address and command inputs is measured between VIH and VIL. 16) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter. 17) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 18) tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 19) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 20) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
Data Sheet
47
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Electrical Characteristics
21) A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 22) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period ; round to the next higher integer. 23) tDAL = (tWR / tCK) + (tRP / tCK): for each of the terms above, if not already an integer, round to the next higher integer. 24) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8 * tREFI.
Table 24 Parameter
Output Slew Rate Characteristics 1) Typical Range TBD TBD Minimum 0.7 0.3 0.7 Maximum 2.5 1.0 1.4 Unit V/ns V/ns Notes
2)
Pullup and Pulldown Slew Rate (Full Drive Buffer) Pullup and Pulldown Slew Rate (Half Drive Buffer) Output Slew Rate Matching Ratio (Pullup to Pulldown)
2)
3)
1) Output slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling). 2) The parameter is measured using a 20pF capacitive load connected to VSSQ. 3) The ratio of the pullup slew rate to the pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
Table 25 Parameter
AC Overshoot / Undershoot Specification Maximum 0.9 0.9 3.0 3.0 Unit V V V-ns V-ns Notes - - - -
Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDD Maximum undershoot area below VSS
3.0 Overshoot 2.5 2.0 1.5
Voltage (V)
VDD
1.0 0.5 0 -0.5 -1.0 -1.5 0 1
Max. Amplitude = 0.9V
Max. Area = 3V-ns
VSS
Undershoot
2
3 time (ns)
4
5
6
7
Figure 39
AC Overshoot and Undershoot Definition
Data Sheet
48
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3.3
Table 26
Operating Currents
Maximum Operating Currents1)2)3)4)5) Symbol Value Unit - 7.5
Parameter & Test Conditions Operating one bank active-precharge current:
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE
IDD0 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4R IDD4W IDD5 IDD6 IDD8
50
mA
Precharge power-down standby current:
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
2.2
mA
Precharge power-down standby current with clock stop:
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
2.1
mA
Precharge non power-down standby current:
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
15
mA
Precharge non power-down standby current with clock stop:
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
2.6
mA
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
2.3
mA
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
2.2
mA
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
22
mA
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
2.7
mA
Operating burst read current:
one bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data change each burst transfer
75
mA
Operating burst write current:
one bank active; BL = 4; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer
75
mA
Auto-Refresh current:
tRC = tRFCmin; tCK = tCKmin; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
135
mA
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE; data bus inputs are STABLE
2
mA
Deep Power Down current 1) 0 C TC 70 C (comm.); VDD = VDDQ = 1.70 V - 1.90 V.
506)
A
Recommended Operating Conditions unless otherwise noted 2) IDD specifications are tested after the device is properly intialized and measured at 133 MHz for -7.5 speed grade. 3) Input slew rate is 1.0 V/ns.
Data Sheet
49
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Electrical Characteristics
4) Definitions for IDD: LOW is defined as VIN 0.1 * VDDQ ; HIGH is defined as VIN 0.9 * VDDQ ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE 5) All parameters are measured with no output loads. 6) IDD8 current is typical.
Data Sheet
50
Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
HYB18M512160BFX 512-Mbit DDR Mobile-RAM
Package Outlines
4
Package Outlines
Figure 40
P-VFBGA-60-1 (Plastic Very Thin Fine Ball Grid Array Package)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 51 Dimensions in mm Rev. 1.10, 2006-11 04052006-4SYQ-ZRN3
Data Sheet
Edition 2006-11 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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